The present invention relates to a method of manufacturing a semiconductor integrated circuit device and to semiconductor integrated circuit device technology; and, more specifically, the invention relates to a technology suitably applicable to the manufacture of semiconductor integrated circuit devices having a structure in which n-channel MIS (metal insulator semiconductor) transistors and p-channel MIS transistors are provided on the same semiconductor substrate.
An effective way to improve the level of integration and the drive capability of the MIS transistors is miniaturization, which in recent years has progressed rapidly.
With the advancement of miniaturization, however, various problems have surfaced. Because the supply voltage remains constant (i.e. the supply voltage is not decreased) while the MIS transistors are manufactured in increasingly fine patterns, the field intensity in the devices increases, which in turn has adverse effects, such as a short channel effect, on the device characteristics.
The short channel effect is an undesired phenomenon in which, as the channel length decreases, the area affected by a drain voltage increases to cover an area immediately below a gate electrode, pulling down the potential of the semiconductor substrate surface, and resulting in variations (fall) of threshold voltage and reduction in the actual channel length.
When this short channel effect becomes more significant, the drain current can no longer be controlled by the gate voltage-a so-called punch-through phenomenon that will cause an increased leakage current between source and drain. The punch-through thus causes degradation of, for example, the memory retention capability in the transfer gate of a DRAM (dynamic random access memory).
Technologies to avoid these problems have been proposed which, for example, provide at the end portions of the source and the drain of a MIS transistor, on the channel side, a semiconductor region of a high impurity concentration of the same conduction type as the impurity of the channel. Such a punch-through suppression technology is disclosed, for example, in Japanese Patent Laid-Open No. 136404/1993.
For CMOS transistors comprising an n-channel MISFET (hereinafter referred to as nMOS) and a p-channel MISFET (pMOS), a CMOS manufacturing method is disclosed in Japanese Patent Laid-Open No. 111461/1996, which provides a so-called pocket ion-implanted region to suppress the punch-through phenomenon.
This publication discloses the following method of fabrication. After nMOS and pMOS gate electrodes are formed, a first mask is formed that exposes the nMOS formation region and covers the pMOS formation. Using this first mask, ion implantation is performed to form a low impurity concentration diffusion layer in the nMOS region, followed by another ion implantation of p-type impurity to cover the front end of the low impurity concentration diffusion layer. Next, a second mask is formed that exposes the pMOS formation region and covers the nMOS formation region. Using this second mask, an ion implantation is carried out to form a low impurity concentration diffusion layer in the pMOS region, followed by another ion implantation of n-type impurity to cover the front end of the low-impurity concentration diffusion layer. Then, a sidewall spacer is formed on the sidewall of the gate electrode. Next, a third mask is formed that exposes the nMOS formation region and covers the pMOS formation region. Using this third mask, an ion is implanted to form a high impurity concentration diffusion layer in the nMOS region. Next, a fourth mask is formed that exposes the pMOS formation region and covers the nMOS formation region. Using this fourth mask, an ion implantation is performed to form a high impurity concentration diffusion layer in the pMOS region.
With the above fabrication method, a CMOS can be provided that has an LDD structure and a pocket ion-implanted region for prevention of punch-through.
In studies by the inventor of this invention, it has been found that the above ion implantation requires at least four masks.
This means that a photolithography process must be performed four times, giving rise to a problem of too many photomasks and too many photoresist forming and removing processes.
As the number of processes for forming and removing photoresist increases, the process of making a semiconductor integrated circuit device becomes complex and the chance of foreign matter adhering to the device increases, thereby deteriorating the manufacturing yield and reliability of the semiconductor integrated circuit device.
An object of the present invention is to provide a technology that can reduce the number of manufacturing processes for making a semiconductor integrated circuit device having a structure in which n-channel MIS transistors and p-channel MIS transistors are formed on the same semiconductor substrate.
Another object of this invention is to provide a technology that can reduce the number of photomasks used in the process of making a semiconductor integrated circuit device having a structure in which n-channel MIS transistors and p-channel MIS transistors are formed on the same semiconductor substrate.
Still another object of this invention is to provide a technology that can improve the yield and reliability of a semiconductor integrated circuit device having a structure in which n-channel MIS transistors and p-channel MIS transistors are formed on the same semiconductor substrate.
A further object of this invention is to provide a technology that can reduce the number of processes used in making a semiconductor integrated circuit device, including a DRAM, having memory cells whose memory cell selection MISFETs and capacitors are connected in series.
These and other objects and novel features of this invention will become apparent from the description provided in this specification and the accompanying drawings.
Representative aspects of this invention disclosed in this application may be briefly summarized as follows.
The method of manufacturing a semiconductor integrated circuit device having an n-channel MIS transistor and a p-channel MIS transistor formed in a semiconductor substrate, comprises:
(a) a step of forming a p-well and an n-well in the semiconductor substrate;
(b) a step of forming over the semiconductor substrate a first mask that covers a p-channel MIS transistor formation region and a p-well power supply region and exposes an n-channel MIS transistor formation region and an n-well power supply region;
(c) a step of introducing an n type impurity for making an n+ type semiconductor region into a region of the semiconductor substrate exposed from the first mask;
(d) a step of introducing a p type impurity for making a pxe2x88x92 type semiconductor region into a region of the semiconductor substrate exposed from the first mask in an inclined direction with respect to the principal surface of the semiconductor substrate;
(e) a step of forming over the semiconductor substrate a second mask that covers an n-channel MIS transistor formation region and an n-well power supply region and exposes a p-channel MIS transistor formation region and a p-well power supply region;
(f) a step of introducing a p type impurity for making a p+ type semiconductor region into a region of the semiconductor substrate exposed from the second mask; and
(g) a step of introducing an n type impurity for making an nxe2x88x92 type semiconductor region into a region of the semiconductor substrate exposed from the second mask in an inclined direction with respect to the principal surface of the semiconductor substrate.
The method of manufacturing a semiconductor integrated circuit device further comprises:
(a) a step of introducing an n type impurity for making an nxe2x88x92 type semiconductor region into a region of the semiconductor substrate exposed from the first mask; and
(b) a step of introducing a p type impurity for making a pxe2x88x92 type semiconductor region into a region of the semiconductor substrate exposed from the second mask.
In the method of manufacturing a semiconductor integrated circuit device of this invention,
(a) in the step of forming the first mask, the first mask is so formed as to cover a memory cell area of the semiconductor substrate, too; and
(b) in the step of forming the second mask, the second mask is so formed as to cover other than the well power supply region in the memory cell area of the semiconductor substrate.
Further, in the method of manufacturing a semiconductor integrated circuit device having a p type first semiconductor region and an n type second semiconductor region in a semiconductor substrate, in which the p type first semiconductor region has an n-channel MISFET and the n type second semiconductor region has a p-channel MISFET, the manufacturing method of this invention comprises:
(a) a step of forming a gate insulation film over a principal surface of the semiconductor substrate;
(b) a step of forming a gate electrode having a sidewall over the gate insulation film on the principal surface of the p type first semiconductor region and the n type second semiconductor region;
(c) a step of forming a sidewall insulation film over the sidewall of the gate electrode;
(d) a step of forming a first mask over the semiconductor substrate -that exposes the n-channel MISFET formation region and covers the p-channel MISFET formation region;
(e) a step of ion-implanting into regions of the semiconductor substrate exposed from the first mask a p type first impurity for making a third semiconductor region, an n type second impurity for making a fourth semiconductor region, and an n type third impurity for making a fifth semiconductor region;
(f) a step of forming a second mask over the semiconductor substrate that exposes the p-channel MISFET formation region and covers the n-channel MISFET formation region; and
(g) a step of ion-implanting into regions of the semiconductor substrate exposed from the second mask an n type fourth impurity for making a sixth semiconductor region, a p type fifth impurity for making a seventh semiconductor region, and a p type sixth impurity for making an eighth semiconductor region.
Further, in the method of manufacturing a semiconductor integrated circuit device having a p type first semiconductor region, an n type second semiconductor region and a p type ninth semiconductor region in a semiconductor substrate, in which the p type first semiconductor region has an n-channel MISFET and a first power supply region for supplying a first fixed voltage to the p type first semiconductor region, in which the n type second semiconductor region has a p-channel MISFET and a second power supply region for supplying a second fixed voltage to the n type second semiconductor region, and in which the p type ninth semiconductor region has a memory cell area and a third power supply region for supplying a third fixed voltage to the p type ninth semiconductor region; the manufacturing method of this invention comprises:
(a) a step of forming a gate insulation film over a principal surface of the semiconductor substrate;
(b) a step of forming a gate electrode having a sidewall over the gate insulation film on the principal surface of the p type first semiconductor region, the n type second semiconductor region and the p type ninth semiconductor region;
(c) a step of forming a sidewall insulation film over the sidewall of the gate electrode;
(d) a step of forming a first mask over the semiconductor substrate that exposes the n-channel MISFET formation region and the second power supply region and covers the p-channel MISFET formation region, the first power supply region, the third power supply region and the memory cell region;
(e) a step of ion-implanting into regions of the semiconductor substrate exposed from the first mask a p type first impurity for making a third semiconductor region, an-n type second impurity for making a fourth semiconductor region, and an n type third impurity for making a fifth semiconductor region;
(f) a step of forming a second mask over the semiconductor substrate that exposes the p-channel MISFET formation region, the first power supply region and the third power supply region and covers the n-channel MISFET formation region, the second power supply region and the memory cell area; and
(g) a step of ion-implanting into regions of the semiconductor substrate exposed from the second mask an n type fourth impurity for making a sixth semiconductor region, a p type fifth impurity for making a seventh semiconductor region, and a p type sixth impurity for making an eighth semiconductor region;
wherein the n type third impurity is ion-implanted to a location deeper than the p type first impurity and the p type sixth impurity is ion-implanted to a location deeper than the n type fourth impurity.
Further, in the method of manufacturing a semiconductor integrated circuit device of this invention, the n type third impurity is ion-implanted at a higher concentration than the n type second impurity, and the p type sixth impurity is ion-implanted at a higher concentration than the p type fifth impurity.
Further, in the method of manufacturing a semiconductor integrated circuit device of this invention, the n type third impurity is ion-implanted at a first inclination with respect to a direction perpendicular to the principal surface of the semiconductor substrate, the p type first impurity and the n type second impurity are ion-implanted at a second inclination with respect to the direction perpendicular to the principal surface of the semiconductor substrate, the second inclination is greater than the first inclination, the p type sixth impurity is ion-implanted at a third inclination with respect to the direction perpendicular to the principal surface of the semiconductor substrate, the n type fourth impurity and the p type fifth impurity are ion-implanted at a fourth inclination with respect to the direction perpendicular to the principal surface of the semiconductor substrate, and the fourth inclination is greater than the third inclination.
Further, in the method of manufacturing a semiconductor integrated circuit device of this invention, in the first power supply region and the third power supply region, the eighth semiconductor region is formed to cover the sixth semiconductor region and the seventh semiconductor region, and in the second power supply region the fifth semiconductor region is formed to cover the third semiconductor region and the fourth semiconductor region.